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Low Distortion Differential ADC Driver AD8138
FEATURES
Easy to use, single-ended-to-differential conversion Adjustable output common-mode voltage Externally adjustable gain Low harmonic distortion -94 dBc SFDR @ 5 MHz -85 dBc SFDR @ 20 MHz -3 dB bandwidth of 320 MHz, G = +1 Fast settling to 0.01% of 16 ns Slew rate 1150 V/s Fast overdrive recovery of 4 ns Low input voltage noise of 5 nV/Hz 1 mV typical offset voltage Wide supply range +3 V to 5 V Low power 90 mW on 5 V 0.1 dB gain flatness to 40 MHz Available in 8-Lead SOIC and MSOP packages
PIN CONFIGURATION
-IN 1 VOCM 2 V+ 3 +OUT 4
8 7 6
+IN NC V-
01073-001
AD8138
Figure 1.
5
-OUT
NC = NO CONNECT
TYPICAL APPLICATION CIRCUIT
5V 499 VIN 499 VOCM 499 + AIN AIN 499 AVDD DVDD DIGITAL OUTPUTS VREF
01073-002
5V
AD8138
-
ADC
AVSS
Figure 2.
APPLICATIONS
ADC drivers Single-ended-to-differential converters IF and baseband gain blocks Differential buffers Line drivers
GENERAL DESCRIPTION
The AD8138 is a major advancement over op amps for differential signal processing. The AD8138 can be used as a single-ended-to-differential amplifier or as a differential-todifferential amplifier. The AD8138 is as easy to use as an op amp and greatly simplifies differential signal amplification and driving. Manufactured on ADI's proprietary XFCB bipolar process, the AD8138 has a -3 dB bandwidth of 320 MHz and delivers a differential signal with the lowest harmonic distortion available in a differential amplifier. The AD8138 has a unique internal feedback feature that provides balanced output gain and phase matching, suppressing even order harmonics. The internal feed-back circuit also minimizes any gain error that would be associated with the mismatches in the external gain setting resistors. The AD8138's differential output helps balance the input to differential ADCs, maximizing the performance of the ADC. The AD8138 eliminates the need for a transformer with high performance ADCs, preserving the low frequency and dc information. The common-mode level of the differential output is adjustable by a voltage on the VOCM pin, easily level-shifting the input signals for driving single-supply ADCs. Fast overload recovery preserves sampling accuracy. The AD8138 distortion performance makes it an ideal ADC driver for communication systems, with distortion performance good enough to drive state-of-the-art 10-bit to 16-bit converters at high frequencies. The AD8138's high bandwidth and IP3 also make it appropriate for use as a gain block in IF and baseband signal chains. The AD8138 offset and dynamic performance makes it well suited for a wide variety of signal processing and data acquisition applications. The AD8138 is available in both SOIC and MSOP packages for operation over -40C to +85C temperatures.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
AD8138 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Pin Configuration............................................................................. 1 Typical Application Circuit ............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 DIN to OUT Specifications...................................................... 3 VOCM to OUT Specifications ..................................................... 4 DIN to OUT Specifications...................................................... 5 VOCM to OUT Specifications ..................................................... 6 Absolute Maximum Ratings............................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ............................................. 9 Test Circuits..................................................................................... 15 Operational Description................................................................ 16 Definition of Terms.................................................................... 16 Theory of Operation ...................................................................... 17 Analyzing an Application Circuit ............................................ 17 Setting the Closed-Loop Gain .................................................. 17 Estimating the Output Noise Voltage ...................................... 17 The Impact of Mismatches in the Feedback Networks ......... 18 Calculating an Application Circuit's Input Impedance......... 18 Input Common-Mode Voltage Range in Single-Supply Applications ................................................................................ 18 Setting the Output Common-Mode Voltage .......................... 18 Driving a Capacitive Load......................................................... 18 Layout, Grounding, and Bypassing.............................................. 19 Balanced Transformer Driver ....................................................... 20 High Performance ADC Driving ................................................. 21 3 V Operation ................................................................................. 22 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 23
REVISION HISTORY
1/06--Rev. E to Rev. F Changes to Features.......................................................................... 1 Added Thermal Resistance Section and Maximum Power Dissipation Section........................................................................... 7 Changes to Balanced Transformer Driver Section..................... 20 Changes to Ordering Guide .......................................................... 23 3/03--Rev. D to Rev. E Changes to Specifications ................................................................ 2 Changes to Ordering Guide ............................................................ 4 Changes to TPC 16........................................................................... 6 Changes to Table I ............................................................................ 9 Added New Paragraph after Table I ............................................. 10 Updated Outline Dimensions ....................................................... 14
7/02--Rev. C to Rev. D Addition of TPC 35 and TPC 36 .....................................................8 6/01--Rev. B to Rev. C Edits to Specifications ......................................................................2 Edits to Ordering Guide ...................................................................4 12/00--Rev. A to Rev. B 9/99--Rev. 0 to Rev. A 3/99--Rev. 0: Initial Version
Rev. F | Page 2 of 24
AD8138 SPECIFICATIONS
DIN to OUT SPECIFICATIONS
At 25C, VS = 5 V, VOCM = 0, G = +1, RL, dm = 500 , unless otherwise noted. Refer to Figure 39 for test setup and label descriptions. All specifications refer to single-ended input and differential outputs, unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth Bandwidth for 0.1 dB Flatness Large Signal Bandwidth Slew Rate Settling Time Overdrive Recovery Time NOISE/HARMONIC PERFORMANCE 1 Second Harmonic Conditions VOUT = 0.5 V p-p, CF = 0 pF VOUT = 0.5 V p-p, CF = 1 pF VOUT = 0.5 V p-p, CF = 0 pF VOUT = 2 V p-p, CF = 0 pF VOUT = 2 V p-p, CF = 0 pF 0.01%, VOUT = 2 V p-p, CF = 1 pF VIN = 5 V to 0 V step, G = +2 VOUT = 2 V p-p, 5 MHz, RL, dm = 800 VOUT = 2 V p-p, 20 MHz, RL, dm = 800 VOUT = 2 V p-p, 70 MHz, RL, dm = 800 VOUT = 2 V p-p, 5 MHz, RL, dm = 800 VOUT = 2 V p-p, 20 MHz, RL, dm = 800 VOUT = 2 V p-p, 70 MHz, RL, dm = 800 20 MHz 20 MHz f = 100 kHz to 40 MHz f = 100 kHz to 40 MHz VOS, dm = VOUT, dm/2; VDIN+ = VDIN- = VOCM = 0 V TMIN to TMAX variation TMIN to TMAX variation Differential Common mode -2.5 Min 290 Typ 320 225 30 265 1150 16 4 -94 -87 -62 -114 -85 -57 -77 37 5 2 1 4 3.5 -0.01 6 3 1 -4.7 to +3.4 -77 7.75 95 -66 +2.5 7 Max Unit MHz MHz MHz MHz V/s ns ns dBc dBc dBc dBc dBc dBc dBc dBm nV/Hz pA/Hz mV V/C A A/C M M pF V dB V p-p mA dB
Third Harmonic
IMD IP3 Voltage Noise (RTI) Input Current Noise INPUT CHARACTERISTICS Offset Voltage Input Bias Current Input Resistance Input Capacitance Input Common-Mode Voltage CMRR OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Output Balance Error
1
VOUT, dm/VIN, cm; VIN, cm = 1 V Maximum VOUT; single-ended output VOUT, cm/VOUT, dm; VOUT, dm = 1 V
-70
Harmonic distortion performance is equal or slightly worse with higher values of RL, dm. See Figure 17 and Figure 18 for more information.
Rev. F | Page 3 of 24
AD8138
VOCM to OUT SPECIFICATIONS
At 25C, VS = 5 V, VOCM = 0, G = +1, RL, dm = 500 , unless otherwise noted. Refer to Figure 39 for test setup and label descriptions. All specifications refer to single-ended input and differential outputs, unless otherwise noted. Table 2.
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Slew Rate INPUT VOLTAGE NOISE (RTI) DC PERFORMANCE Input Voltage Range Input Resistance Input Offset Voltage Input Bias Current VOCM CMRR Gain POWER SUPPLY Operating Range Quiescent Current Power Supply Rejection Ratio OPERATING TEMPERATURE RANGE Conditions Min Typ 250 330 17 3.8 200 1 0.5 -75 1 Max Unit MHz V/s nV/Hz V k mV A dB V/V V mA A/C dB C
f = 0.1 MHz to 100 MHz
VOS, cm = VOUT, cm; VDIN+ = VDIN- = VOCM = 0 V VOUT, dm/VOCM; VOCM = 1 V VOUT, cm/VOCM; VOCM = 1 V
-3.5
+3.5
0.9955 1.4 18
1.0045 5.5 23 -70 +85
TMIN to TMAX variation VOUT, dm/VS; VS = 1 V -40
20 40 -90
Rev. F | Page 4 of 24
AD8138
DIN to OUT SPECIFICATIONS
At 25C, VS = 5 V, VOCM = 2.5 V, G = +1, RL, dm = 500 , unless otherwise noted. Refer to Figure 39 for test setup and label descriptions. All specifications refer to single-ended input and differential output, unless otherwise noted. Table 3.
Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth Bandwidth for 0.1 dB Flatness Large Signal Bandwidth Slew Rate Settling Time Overdrive Recovery Time NOISE/HARMONIC PERFORMANCE 1 Second Harmonic Conditions VOUT = 0.5 V p-p, CF = 0 pF VOUT = 0.5 V p-p, CF = 1 pF VOUT = 0.5 V p-p, CF = 0 pF VOUT = 2 V p-p, CF = 0 pF VOUT = 2 V p-p, CF = 0 pF 0.01%, VOUT = 2 V p-p, CF = 1 pF VIN = 2.5 V to 0 V step, G = +2 VOUT = 2 V p-p, 5 MHz, RL, dm = 800 VOUT = 2 V p-p, 20 MHz, RL, dm = 800 VOUT = 2 V p-p, 70 MHz, RL, dm = 800 VOUT = 2 V p-p, 5 MHz, RL, dm = 800 VOUT = 2 V p-p, 20 MHz, RL, dm = 800 VOUT = 2 V p-p, 70 MHz, RL, dm = 800 20 MHz 20 MHz f = 100 kHz to 40 MHz f = 100 kHz to 40 MHz VOS, dm = VOUT, dm/2; VDIN+ = VDIN- = VOCM = 0 V TMIN to TMAX variation TMIN to TMAX variation Differential Common mode -2.5 Min 280 Typ 310 225 29 265 950 16 4 -90 -79 -60 -100 -82 -53 -74 35 5 2 1 4 3.5 -0.01 6 3 1 -0.3 to +3.2 -77 2.9 95 -65 +2.5 7 Max Unit MHz MHz MHz MHz V/s ns ns dBc dBc dBc dBc dBc dBc dBc dBm nV/Hz pA/Hz mV V/C A A/C M M pF V dB V p-p mA dB
Third Harmonic
IMD IP3 Voltage Noise (RTI) Input Current Noise INPUT CHARACTERISTICS Offset Voltage Input Bias Current Input Resistance Input Capacitance Input Common-Mode Voltage CMRR OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Output Balance Error
1
VOUT, dm/VIN, cm; VIN, cm = 1 V Maximum VOUT; single-ended output VOUT, cm/VOUT, dm; VOUT, dm = 1 V
-70
Harmonic distortion performance is equal or slightly worse with higher values of RL, dm. See Figure 17 and Figure 18 for more information.
Rev. F | Page 5 of 24
AD8138
VOCM TO OUT SPECIFICATIONS
At 25C, VS = 5 V, VOCM = 2.5 V, G = +1, RL, dm = 500 , unless otherwise noted. Refer to Figure 39 for test setup and label descriptions. All specifications refer to single-ended input and differential output, unless otherwise noted. Table 4.
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Slew Rate INPUT VOLTAGE NOISE (RTI) DC PERFORMANCE Input Voltage Range Input Resistance Input Offset Voltage Input Bias Current VOCM CMRR Gain POWER SUPPLY Operating Range Quiescent Current Power Supply Rejection Ratio OPERATING TEMPERATURE RANGE Conditions Min Typ 220 250 17 1.0 to 3.8 100 1 0.5 -70 1 Max Unit MHz V/s nV/Hz V k mV A dB V/V V mA A/C dB C
f = 0.1 MHz to 100 MHz
VOS, cm = VOUT, cm; VDIN+ = VDIN- = VOCM = 0 V VOUT, dm/VOCM; VOCM = 2.5 V 1 V VOUT, cm/VOCM; VOCM = 2.5 V 1 V
-5
+5
0.9968 2.7 15
1.0032 11 21 -70 +85
TMIN to TMAX variation VOUT, dm/VS; VS = 1 V -40
20 40 -90
Rev. F | Page 6 of 24
AD8138 ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Supply Voltage VOCM Internal Power Dissipation Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature Ratings 5.5 V VS 550 mW -40C to +85C -65C to +150C 300C 150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). The load current consists of the differential and common-mode currents flowing to the load, as well as currents flowing through the external feedback networks and internal common-mode feedback loop. The internal resistor tap used in the common-mode feedback loop places a negligible differential load on the output. RMS voltages and currents should be considered when dealing with ac signals. Airflow reduces JA. In addition, more metal directly in contact with the package leads from metal traces through holes, ground, and power planes reduces the JA. Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 8-lead SOIC (121C/W) and 8-lead MSOP (JA = 145C/W) packages on a JEDEC standard 4-layer board. JA values are approximations.
1.75 1.50 1.25 1.00 0.75
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, JA is specified for the device soldered in a circuit board in still air. Table 6.
Package Type 8-Lead SOIC/4-Layer 8-Lead MSOP/4-Layer JA 121 145 Unit C/W C/W
MAXIMUM POWER DISSIPATION (W)
Maximum Power Dissipation
The maximum safe power dissipation in the AD8138 packages is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8138. Exceeding a junction temperature of 150C for an extended period can result in changes in the silicon devices, potentially causing failure.
SOIC
MSOP
0.50 0.25
01073-049
0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (C)
Figure 3. Maximum Power Dissipation vs. Temperature
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. F | Page 7 of 24
AD8138 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
-IN 1 VOCM 2 V+ 3 +OUT 4
8 7 6
+IN NC V-
01073-004
AD8138
5
-OUT
NC = NO CONNECT
Figure 4. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 Mnemonic -IN VOCM V+ +OUT -OUT V- NC +IN Description Negative Input Summing Node. Voltage applied to this pin sets the common-mode output voltage with a ratio of 1:1. For example, 1 V dc on VOCM sets the dc bias level on +OUT and -OUT to 1 V. Positive Supply Voltage. Positive Output. Note that the voltage at -DIN is inverted at +OUT (see Figure 42). Negative Output. Note that the voltage at +DIN is inverted at -OUT (see Figure 42). Negative Supply Voltage. No Connect. Positive Input Summing Node.
Rev. F | Page 8 of 24
AD8138 TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, Gain = 1, RG = RF = RL, dm = 499 V, TA = 25C; refer to Figure 39 for test setup.
6 VIN = 0.2V p-p CF = 0pF 3 VS = +5V 6 VIN = 2V p-p CF = 0pF
3 VS = +5V 0 VS = 5V -3
GAIN (dB)
VS = 5V -3
-6
GAIN (dB)
0
-6
01073-005
1
10 100 FREQUENCY (MHz)
1000
1
10 100 FREQUENCY (MHz)
1000
Figure 5. Small Signal Frequency Response
6 VS = 5V VIN = 0.2V p-p 3 CF = 0pF 3 6
Figure 8. Large Signal Frequency Response
VIN = 2V p-p VS = 5V
CF = 0pF
GAIN (dB)
CF = 1pF -3
GAIN (dB)
0
0 CF = 1pF -3
-6
-6
01073-006
1
10 100 FREQUENCY (MHz)
1000
1
10 100 FREQUENCY (MHz)
1000
Figure 6. Small Signal Frequency Response
0.5 VS = 5V VIN = 0.2V p-p 0.3 CF = 0pF 20 30
Figure 9. Large Signal Frequency Response
G = 10, RF = 4.99k G = 5, RF = 2.49k
VS = 5V CF = 0pF VOUT, dm = 0.2V p-p RG = 499
GAIN (dB)
GAIN (dB)
0.1
10 G = 2, RF = 1k G = 1, RF = 499
-0.1 CF = 1pF -0.3
0
01073-007
1
10 FREQUENCY (MHz)
100
1
10 100 FREQUENCY (MHz)
1000
Figure 7. 0.1 dB Flatness vs. Frequency
Figure 10. Small Signal Frequency Response for Various Gains
Rev. F | Page 9 of 24
01073-010
-0.5
-10
01073-009
-9
-9
01073-008
-9
-9
AD8138
-50 -60 -70 VOUT, dm = 2V p-p RL = 800 -60 VS = 5V RL = 800 -70 HD2 (F = 20MHz) HD2 (VS = +5V) -80 -90 -100 -110 HD3 (VS = 5V)
01073-011
HD3 (F = 20MHz)
DISTORTION (dBc)
HD2 (V S = 5V)
DISTORTION (dBc)
-80
-90 HD2 (F = 5MHz) -100 HD3 (F = 5MHz)
HD3 (VS = +5V) -110
0
10
20 30 40 50 FUNDAMENTAL FREQUENCY (MHz)
60
70
0
1 2 3 4 5 DIFFERENTIAL OUTPUT VOLTAGE (V p-p)
6
Figure 11. Harmonic Distortion vs. Frequency
-40 -50 -60
Figure 14. Harmonic Distortion vs. Differential Output Voltage
-60 VS = 5V RL = 800 -70 HD2 (F = 20MHz)
DISTORTION (dBc)
VOUT, dm = 4V p-p RL = 800 HD3 (V S = +5V)
DISTORTION (dBc)
-80 HD3 (F = 20MHz) -90 HD2 (F = 5MHz) -100 HD3 (F = 5MHz)
-70 -80 -90 -100 -110 0 10 20 30 40 50 FUNDAMENTAL FREQUENCY (MHz) 60 70 HD2 (VS = +5V) HD2 (V S = 5V)
HD3 (VS = 5V)
01073-012
-110
0
1 2 3 DIFFERENTIAL OUTPUT VOLTAGE (V p-p)
4
Figure 12. Harmonic Distortion vs. Frequency
-30 -40 -50 -60 -70 -80 -90 -100 HD3 (VS = +5V)
Figure 15. Harmonic Distortion vs. Differential Output Voltage
-60
VOUT, dm = 2V p-p RL = 800 FO = 20MHz
VS = 3V RL = 800 HD3 (F = 20MHz) HD2 (F = 20MHz)
-70
DISTORTION (dBc)
DISTORTION (dBc)
HD2 (VS = +5V)
-80
-90 HD2 (F = 5MHz)
HD3 (VS = 5V)
-100
HD2 (VS = 5V)
HD3 (F = 5MHz)
01073-013
-4
-3
-2
0 1 VOCM DC OUTPUT (V)
-1
2
3
4
0.50 0.75 1.00 1.25 1.50 DIFFERENTIAL OUTPUT VOLTAGE (V p-p)
1.75
Figure 13. Harmonic Distortion vs. VOCM
Figure 16. Harmonic Distortion vs. Differential Output Voltage
Rev. F | Page 10 of 24
01073-016
-110 0.25
01073-015
-120
01073-014
-120
-120
AD8138
-60 VS = 5V VOUT, dm = 2V p-p -70
45
RL = 800
40
DISTORTION (dBc)
-80 HD3 (F = 20MHz) -90 HD2 (F = 5MHz) -100 HD3 (F = 5MHz)
01073-020
INTERCEPT (dBm)
HD2 (F = 20MHz)
VS = 5V 35 VS = +5V 30
01073-017
-110 200
25 0 20 40 FREQUENCY (MHz) 60 80
600
1000 RLOAD ()
1400
1800
Figure 17. Harmonic Distortion vs. RLOAD
-60 VS = 5V VOUT, dm = 2V p-p -70 HD2 (F = 20MHz)
DISTORTION (dBc)
Figure 20. Third-Order Intercept vs. Frequency
VS = 5V
VOUT, dm
-80
HD3 (F = 20MHz)
VOUT-
-90 HD2 (F = 5MHz) -100 HD3 (F = 5MHz)
1V 5ns V+DIN
VOUT+
600
1000 RLOAD ()
1400
1800
01073-018
-120 200
Figure 18. Harmonic Distortion vs. RLOAD
10 FC = 50MHz VS = 5V -10
Figure 21. Large Signal Transient Response
CF = 0pF
VOUT, dm = 0.2V p-p VS = 5V
-30
POUT (dBm)
CF = 1pF
-50
-70
40mV
5ns
49.7
49.9 50.1 FREQUENCY (MHz)
50.3
50.5
01073-019
-110 49.5
Figure 19. Intermodulation Distortion
Figure 22. Small Signal Transient Response
Rev. F | Page 11 of 24
01073-022
-90
01073-021
-110
AD8138
VS = 5V VOUT, dm = 2V p-p CF = 0pF
VOUT, dm
VS = +5V
VS = 5V F = 20MHz V+DIN = 8V p-p G = 3 (RF = 1500)
V+DIN
01073-023
01073-026 01073-028
400mV
5ns
4V
30ns
Figure 23. Large Signal Transient Response
Figure 26. Output Overdrive
CF = 0pF
VOUT, dm = 2V p-p VS = 5V
VS = 5V CF = 0pF CL = 5pF
CL = 10pF
CF = 1pF
CL = 20pF
01073-024
400mV
5ns
400mV
2.5ns
Figure 24. Large Signal Transient Response
Figure 27. Large Signal Transient Response for Various Cap Loads (See Figure 40)
-20
200V VOUT, dm
VS = 5V CF = 1pF
VS = 5V VOUT, dm/VIN, cm -30
-40
CMRR (dB)
-50
-60
V+DIN
01073-025
-70
1V
4ns
1
10 100 FREQUENCY (MHz)
1k
Figure 25. Settling Time
Figure 28. CMRR vs. Frequency
Rev. F | Page 12 of 24
01073-029
-80
AD8138
-20 VIN = 2V p-p -30 DIFFERENTIAL OUTPUT OFFSET (mV)
5.0
BALANCE ERROR (dB)
2.5 VS = 5V VS = +5V
-40 VS = 5V
0
-50
VS = +3V -2.5
-60
VS = +5V
01073-031
1
10 100 FREQUENCY (MHz)
1k
-20
0
20 40 TEMPERATURE (C)
60
80
100
Figure 29. Output Balance Error vs. Frequency (See Figure 41)
-10 VOUT, dm/VS -20 -30 -40 -50 -60 -70 -80
01073-032
Figure 32. Output Referred Differential Offset Voltage vs. Temperature
5
BIAS CURRENT (A)
-PSRR (VS = 5V)
4 VS = 5V, +5V 3 VS = +3V 2
PSRR (dB)
+PSRR (VS = +5V, 0V AND 5V)
1
10 100 FREQUENCY (MHz)
1k
-20
0
20 40 60 TEMPERATURE (C)
80
100
Figure 30. PSRR vs. Frequency
100 SINGLE-ENDED OUTPUT 30
Figure 33. Input Bias Current vs. Temperature
25
SUPPLY CURRENT (mA)
IMPEDANCE ()
10
VS = 5V 20 VS = +5V VS = +3V 10
VS = +5V
15
1 VS = 5V
01073-033
1
10 FREQUENCY (MHz)
100
-20
0
20 40 60 TEMPERATURE (C)
80
100
Figure 31. Output Impedance vs. Frequency
Figure 34. Supply Current vs. Temperature
Rev. F | Page 13 of 24
01073-036
0.1
5 -40
01073-035
-90
1 -40
01073-034
-70
-5.0 -40
AD8138
6 VS = +5V 3
INPUT CURRENT NOISE (pA/ Hz)
100
VS = 5V
GAIN (dB)
0
10
-3
1.1pA/ Hz
-6
01073-037
1
10 100 FREQUENCY (MHz)
1k
10
100
1k 10k FREQUENCY (Hz)
100k
1M
Figure 35. VOCM Frequency Response
1000
VS = 5V VOCM = -1V TO +1V VOUT, cm
Figure 37. Current Noise (RTI)
INPUT VOLTAGE NOISE (nV/ Hz)
100
10
5.7nV/ Hz
01073-038
400mV
5ns
10
100
1k 10k FREQUENCY (Hz)
100k
1M
Figure 36. VOCM Transient Response
Figure 38. Voltage Noise (RTI)
Rev. F | Page 14 of 24
01073-040
1
01073-039
-9
1
AD8138 TEST CIRCUITS
RF = 499 RG = 499 49.9 RG = 499 24.9 RF = 499 AD8138 RL, dm = 499
499 49.9 499
01073-003
499 249
AD8138
499
249
01073-030
24.9
Figure 39. Basic Test Circuit
499 499 49.9 499 24.9 24.9
Figure 41. Test Circuit for Output Balance
AD8138
499
24.9
CL
453
01073-027
Figure 40. Test Circuit for Cap Load Drive
Rev. F | Page 15 of 24
AD8138 OPERATIONAL DESCRIPTION
DEFINITION OF TERMS
CF RF RG +IN -OUT
Common-mode voltage refers to the average of two node voltages. The output common-mode voltage is defined as VOUT, cm = (V+OUT + V-OUT)/2 Balance is a measure of how well differential signals are matched in amplitude and exactly 180 apart in phase. Balance is most easily determined by placing a well-matched resistor divider between the differential voltage nodes and comparing the magnitude of the signal at the divider's midpoint with the magnitude of the differential signal (see Figure 41). By this definition, output balance is the magnitude of the output common-mode voltage divided by the magnitude of the output differential mode voltage:
+DIN VOCM -DIN
AD8138
RG -IN RF CF +OUT
RL, dm
VOUT, dm
Figure 42. Circuit Definitions
Differential voltage refers to the difference between two node voltages. For example, the output differential voltage (or equivalently output differential-mode voltage) is defined as VOUT, dm = (V+OUT - V-OUT) where V+OUT and V-OUT refer to the voltages at the +OUT and -OUT terminals with respect to a common reference.
01073-041
Output Balance Error =
VOUT , cm VOUT , dm
Rev. F | Page 16 of 24
AD8138 THEORY OF OPERATION
The AD8138 differs from conventional op amps in that it has two outputs whose voltages move in opposite directions. Like an op amp, it relies on high open-loop gain and negative feedback to force these outputs to the desired voltages. The AD8138 behaves much like a standard voltage feedback op amp and makes it easy to perform single-ended-to-differential conversion, common-mode level-shifting, and amplification of differential signals. Also like an op amp, the AD8138 has high input impedance and low output impedance. Previous differential drivers, both discrete and integrated designs, have been based on using two independent amplifiers and two independent feedback loops, one to control each of the outputs. When these circuits are driven from a single-ended source, the resulting outputs are typically not well balanced. Achieving a balanced output has typically required exceptional matching of the amplifiers and feedback networks. DC common-mode level-shifting has also been difficult with previous differential drivers. Level-shifting has required the use of a third amplifier and feedback loop to control the output common-mode level. Sometimes the third amplifier has also been used to attempt to correct an inherently unbalanced circuit. Excellent performance over a wide frequency range has proven difficult with this approach. The AD8138 uses two feedback loops to separately control the differential and common-mode output voltages. The differential feedback, set with external resistors, controls only the differential output voltage. The common-mode feedback controls only the common-mode output voltage. This architecture makes it easy to arbitrarily set the output common-mode level. It is forced, by internal common-mode feedback, to be equal to the voltage applied to the VOCM input, without affecting the differential output voltage. The AD8138 architecture results in outputs that are very highly balanced over a wide frequency range without requiring tightly matched external components. The common-mode feedback loop forces the signal component of the output common-mode voltage to be zeroed. The result is nearly perfectly balanced differential outputs of identical amplitude and exactly 180 apart in phase.
ANALYZING AN APPLICATION CIRCUIT
The AD8138 uses high open-loop gain and negative feedback to force its differential and common-mode output voltages in such a way as to minimize the differential and common-mode error voltages. The differential error voltage is defined as the voltage between the differential inputs labeled +IN and -IN in Figure 42. For most purposes, this voltage can be assumed to be zero. Similarly, the difference between the actual output commonmode voltage and the voltage applied to VOCM can also be assumed to be zero. Starting from these two assumptions, any application circuit can be analyzed.
SETTING THE CLOSED-LOOP GAIN
Neglecting the capacitors CF, the differential-mode gain of the circuit in Figure 42 can be determined to be described by
VOUT , dm VOUT , dm
=
RF S RG S
This assumes the input resistors, RGS, and feedback resistors, RFS, on each side are equal.
ESTIMATING THE OUTPUT NOISE VOLTAGE
Similar to the case of a conventional op amp, the differential output errors (noise and offset voltages) can be estimated by multiplying the input referred terms, at +IN and -IN, by the circuit noise gain. The noise gain is defined as
R GN = 1 + F R G

To compute the total output referred noise for the circuit of Figure 42, consideration must also be given to the contribution of the Resistors RF and RG. Refer to Table 8 for the estimated output noise voltage densities at various closed-loop gains.
Table 8.
Output Noise AD8138 Only 10 nV/Hz 15 nV/Hz 30 nV/Hz 55 nV/Hz Output Noise AD8138 + RG, RF 11.6 nV/Hz 18.2 nV/Hz 37.9 nV/Hz 70.8 nV/Hz
Gain 1 2 5 10
RG () 499 499 499 499
RF () 499 1.0 k 2.49 k 4.99 k
Bandwidth -3 dB 320 MHz 180 MHz 70 MHz 30 MHz
Rev. F | Page 17 of 24
AD8138
When using the AD8138 in gain configurations where
RF RG
CALCULATING AN APPLICATION CIRCUIT'S INPUT IMPEDANCE
The effective input impedance of a circuit such as the one in Figure 42, at +DIN and -DIN, depends on whether the amplifier is being driven by a single-ended or differential signal source. For balanced differential input signals, the input impedance (RIN, dm) between the inputs (+DIN and -DIN) is simply RIN, dm =2 x RG In the case of a single-ended input signal (for example if -DIN is grounded and the input signal is applied to +DIN), the input impedance becomes
RG = RF 1- 2 x (RG + RF )
of one feedback network is unequal to
RF RG
of the other network, there is a differential output noise due to input-referred voltage in the VOCM circuitry. The output noise is defined in terms of the following feedback terms (refer to Figure 42):
1 = RG RF + RG
RIN , dm
for -OUT to +IN loop, and
2 = RG RF + RG
for +OUT to -IN loop. With these defined,
- 2 VnOUT , dm = 2VnIN ,VOCM 1 1 + 2 where VnOUT, dm is the output differential noise, and VnIN ,VCOM is the input-referred voltage noise in VOCM.
The circuit's input impedance is effectively higher than it would be for a conventional op amp connected as an inverter because a fraction of the differential output voltage appears at the inputs as a common-mode signal, partially bootstrapping the voltage across the input resistor RG.
INPUT COMMON-MODE VOLTAGE RANGE IN SINGLE-SUPPLY APPLICATIONS
The AD8138 is optimized for level-shifting, ground-referenced input signals. For a single-ended input, this would imply, for example, that the voltage at -DIN in Figure 42 would be 0 V when the amplifier's negative power supply voltage (at V-) is also set to 0 V.
THE IMPACT OF MISMATCHES IN THE FEEDBACK NETWORKS
As previously mentioned, even if the external feedback networks (RF/RG) are mismatched, the internal common-mode feedback loop still forces the outputs to remain balanced. The amplitudes of the signals at each output remains equal and 180 out of phase. The input-to-output differential-mode gain varies proportionately to the feedback mismatch, but the output balance is unaffected. Ratio matching errors in the external resistors result in a degradation of the circuit's ability to reject input commonmode signals, much the same as for a four-resistor difference amplifier made from a conventional op amp. In addition, if the dc levels of the input and output commonmode voltages are different, matching errors result in a small differential-mode output offset voltage. For the G = 1 case, with a ground referenced input signal and the output common-mode level set for 2.5 V, an output offset of as much as 25 mV (1% of the difference in common-mode levels) can result if 1% tolerance resistors are used. Resistors of 1% tolerance result in a worstcase input CMRR of about 40 dB, worst-case differential mode output offset of 25 mV due to 2.5 V level-shift, and no significant degradation in output balance error.
SETTING THE OUTPUT COMMON-MODE VOLTAGE
The AD8138's VOCM pin is internally biased at a voltage approximately equal to the midsupply point (average value of the voltages on V+ and V-). Relying on this internal bias results in an output common-mode voltage that is within about 100 mV of the expected value. In cases where more accurate control of the output commonmode level is required, it is recommended that an external source, or resistor divider (made up of 10 k resistors), be used. The output common-mode offset listed in the Specifications section assumes the VOCM input is driven by a low impedance voltage source.
DRIVING A CAPACITIVE LOAD
A purely capacitive load can react with the pin and bondwire inductance of the AD8138, resulting in high frequency ringing in the pulse response. One way to minimize this effect is to place a small capacitor across each of the feedback resistors. The added capacitance should be small to avoid destabilizing the amplifier. An alternative technique is to place a small resistor in series with the amplifier's outputs, as shown in Figure 40.
Rev. F | Page 18 of 24
AD8138 LAYOUT, GROUNDING, AND BYPASSING
As a high speed part, the AD8138 is sensitive to the PCB environment in which it has to operate. Realizing its superior specifications requires attention to various details of good high speed PCB design. The first requirement is for a good solid ground plane that covers as much of the board area around the AD8138 as possible. The only exception to this is that the two input pins (Pin 1 and Pin 8) should be kept a few millimeters from the ground plane, and ground should be removed from inner layers and the opposite side of the board under the input pins. This minimizes the stray capacitance on these nodes and helps preserve the gain flatness vs. frequency. The power supply pins should be bypassed as close as possible to the device to the nearby ground plane. Good high frequency ceramic chip capacitors should be used. This bypassing should be done with a capacitance value of 0.01 F to 0.1 F for each supply. Further away, low frequency bypassing should be provided with 10 F tantalum capacitors from each supply to ground. The signal routing should be short and direct to avoid parasitic effects. Wherever there are complementary signals, a symmetrical layout should be provided to the extent possible to maximize the balance performance. When running differential signals over a long distance, the traces on the PCB should be close together or any differential wiring should be twisted together to minimize the area of the loop that is formed. This reduces the radiated energy and makes the circuit less susceptible to interference.
Rev. F | Page 19 of 24
AD8138 BALANCED TRANSFORMER DRIVER
Transformers are among the oldest devices used to perform a single-ended-to-differential conversion (and vice versa). Transformers can also perform the additional functions of galvanic isolation, step-up or step-down of voltages, and impedance transformation. For these reasons, transformers always find uses in certain applications. However, when driving the transformer in a single-ended manner, there is an imbalance at the output due to the parasitics inherent in the transformer. The primary (or driven) side of the transformer has one side at dc potential (usually ground), while the other side is driven. This can cause problems in systems that require good balance of the transformer's differential output signals. If the interwinding capacitance (CSTRAY) is assumed to be uniformly distributed, a signal from the driving source couples to the secondary output terminal that is closest to the primary's driven side. On the other hand, no signal is coupled to the opposite terminal of the secondary because its nearest primary terminal is not driven (see Figure 43). The exact amount of this imbalance depends on the particular parasitics of the transformer, but is mostly a problem at higher frequencies. The balance of a differential circuit can be measured by connecting an equal-valued resistive voltage divider across the differential outputs and then measuring the center point of the circuit with respect to ground. Since the two differential outputs are supposed to be of equal amplitude, but 180 opposite phase, there should be no signal present for perfectly balanced outputs. The circuit in Figure 43 shows a Mini-Circuits(R) T1-6T transformer connected with its primary driven single-endedly and the secondary connected with a precision voltage divider across its terminals. The voltage divider is made up of two 500 , 0.005% precision resistors. The voltage VUNBAL, which is also equal to the ac common-mode voltage, is a measure of how closely the outputs are balanced. Figure 45 compares the transformer being driven singleendedly by a signal generator and being driven differentially using an AD8138. The top signal trace of Figure 45 shows the balance of the single-ended configuration, while the bottom shows the differentially driven balance response. The 100 MHz balance is 35 dB better when using the AD8138. The well-balanced outputs of the AD8138 provide a drive signal to each of the transformer's primary inputs that are of equal amplitude and 180 out of phase. Therefore, depending on how the polarity of the secondary is connected, the signals that conduct across the interwinding capacitance either both assist the transformer's secondary signal equally, or both buck the secondary signals. In either case, the parasitic effect is symmetrical and provides a well-balanced transformer output (see Figure 45).
SIGNAL IS COUPLED ON THIS SIDE VIA CSTRAY CSTRAY VUNBAL 52.3 PRIMARY 500 0.005% 500 0.005% CSTRAY NO SIGNAL IS COUPLED ON THIS SIDE
01073-042
SECONDARY V DIFF
Figure 43. Transformer Single-Ended-to-Differential Converter Is Inherently Imbalanced
499 CSTRAY 500 0.005% VDIFF 500 0.005%
01073-043
49.9 499 +IN OUT-
VUNBAL
499 -IN
AD8138
OUT+ 49.9 499 CSTRAY
Figure 44. AD8138 Forms a Balanced Transformer Driver
0
OUTPUT BALANCE ERROR (dB)
-20
-40
VUNBAL , FOR TRANSFORMER WITH SINGLE-ENDED DRIVE
-60
-80 VUNBAL , DIFFERENTIAL DRIVE
01073-044
-100 0.3
1
10 FREQUENCY (MHz)
100
500
Figure 45. Output Balance Error for Circuits of Figure 43 and Figure 44
Rev. F | Page 20 of 24
AD8138 HIGH PERFORMANCE ADC DRIVING
The circuit in Figure 46 shows a simplified front-end connection for an AD8138 driving an AD9224, a 12-bit, 40 MSPS ADC. The ADC works best when driven differentially, which minimizes its distortion. The AD8138 eliminates the need for a transformer to drive the ADC and performs singleended-to-differential conversion, common-mode level-shifting, and buffering of the driving signal. The positive and negative outputs of the AD8138 are connected to the respective differential inputs of the AD9224 via a pair of 49.9 resistors to minimize the effects of the switched-capacitor front end of the AD9224. For best distortion performance, it runs from supplies of 5 V. The AD8138 is configured with unity gain for a single-ended, input-to-differential output. The additional 23 , 523 total, at the input to -IN is to balance the parallel impedance of the 50 source and its 50 termination that drives the noninverting input. The signal generator has a ground-referenced, bipolar output, that is, it drives symmetrically above and below ground. Connecting VOCM to the CML pin of the AD9224 sets the output common-mode of the AD8138 at 2.5 V, which is the midsupply level for the AD9224. This voltage is bypassed by a 0.1 F capacitor. The full-scale analog input range of the AD9224 is set to 4 V p-p, by shorting the SENSE terminal to AVSS. This has been determined to be the scaling to provide minimum harmonic distortion. For the AD8138 to swing at 4 V p-p, each output swings 2 V p-p while providing signals that are 180 out of phase. With a common-mode voltage at the output of 2.5 V, each AD8138 output swings between 1.5 V and 3.5 V. A ground-referenced 4 V p-p, 5 MHz signal at DIN+ was used to test the circuit in Figure 46. When the combined-device circuit was run with a sampling rate of 20 MSPS, the spurious-free dynamic range (SFDR) was measured at -85 dBc.
+5V 499 0.1pF
+5V 0.1pF
499 50 SOURCE
3 8 2
+
5
49.9
15 26 24
28
VINB
AVDD
DRVDD
49.9
523
AD8138
4 6
VOCM
AD9224
49.9
23
DIGITAL OUTPUTS DRVSS
27
1
VINA AVSS
16 25
SENSE CML
17 22
0.1pF
499
01073-045
-5V
Figure 46. AD8138 Driving an AD9224, a 12-Bit, 40 MSPS ADC
Rev. F | Page 21 of 24
AD8138 3 V OPERATION
The circuit in Figure 47 shows a simplified front-end connection for an AD8138 driving an AD9203, a 10-bit, 40 MSPS ADC that is specified to work on a single 3 V supply. The ADC works best when driven differentially to make the best use of the signal swing available within the 3 V supply. The appropriate outputs of the AD8138 are connected to the appropriate differential inputs of the AD9203 via a low-pass filter. The AD8138 is configured for unity gain for a single-ended input to differential output. The additional 23 at the input to -IN is to balance the impedance of the 50 source and its 50 termination that drives the noninverting input. The signal generator has ground-referenced, bipolar output, that is, it can drive symmetrically above and below ground. Even though the AD8138 has ground as its negative supply, it can still function as a level-shifter with such an input signal. The output common mode is raised up to midsupply by the voltage divider that biases VOCM. In this way, the AD8138 provides dc coupling and level-shifting of a bipolar signal, without inverting the input signal. The low-pass filter between the AD8138 and the AD9203 provides filtering that helps to improve the signal-to-noise ratio (SNR). Lower noise can be realized by lowering the pole frequency, but the bandwidth of the circuit is lowered.
3V 499 0.1F 3V 0.1F
The circuit was tested with a -0.5 dBFS signal at various frequencies. Figure 48 shows a plot of the total harmonic distortion (THD) vs. frequency at signal amplitudes of 1 V and 2 V differential drive levels.
-40 -45 -50 -55
THD (dBc)
AD8138-2V -60 -65 AD8138-1V -70 -75
01073-047 01073-048
-80 0 5 10 15 FREQUENCY (MHz) 20 25
Figure 48. AD9203 THD @ -0.5 dBFS AD8138
Figure 49 shows the signal-to-noise-plus distortion (SINAD) under the same conditions as above. For the smaller signal swing, the AD8138 performance is quite good, but its performance degrades when trying to swing too close to the supply rails.
65 63 61
0.1F 10k 499 49.9 523
1 3 8 2
+
5
49.9 20pF 49.9 20pF
28 25
2
SINAD (dBc)
AD8138
4 6
AVDD AINN AINP
DRVDD DIGITAL OUTPUTS
59 57 55 53 51 49 47 45 0 5 10 15 FREQUENCY (MHz) 20 25 AD8138-2V AD8138-1V
AD9203
DRVSS
1
26
AVSS
27
0.1F 10k
499
01073-046
Figure 47. AD8138 Driving an AD9203, a 10-Bit, 40 MSPS A/D Converter
Figure 49. AD9203 SINAD @ -0.5 dBFS AD8138
Rev. F | Page 22 of 24
AD8138 OUTLINE DIMENSIONS
5.00 (0.1968) 4.80 (0.1890)
8 5
8
3.20 3.00 2.80
4.00 (0.1574) 3.80 (0.1497) 1
6.20 (0.2440)
4 5.80 (0.2284)
3.20 3.00 2.80
5
1
5.15 4.90 4.65
4
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040)
1.75 (0.0688) 1.35 (0.0532)
0.50 (0.0196) x 45 0.25 (0.0099)
0.95 0.85 0.75
PIN 1 0.65 BSC 1.10 MAX 8 0 0.80 0.60 0.40
0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE
8 0.25 (0.0098) 0 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067)
0.15 0.00
COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.38 0.22 SEATING PLANE
0.23 0.08
COPLANARITY 0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 50. 8-Lead Standard Small Outline Package [SOIC] (R-8) Dimensions shown in millimeters and (inches)
Figure 51. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters
ORDERING GUIDE
Model AD8138AR AD8138AR-REEL AD8138AR-REEL7 AD8138ARZ 1 AD8138ARZ-RL1 AD8138ARZ-R71 AD8138ARM AD8138ARM-REEL AD8138ARM-REEL7 AD8138ARMZ1 AD8138ARMZ-REEL1 AD8138ARMZ-REEL71
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 8-Lead SOIC 8-Lead SOIC, 13" Tape and Reel 8-Lead SOIC, 7" Tape and Reel 8-Lead SOIC 8-Lead SOIC, 13" Tape and Reel 8-Lead SOIC, 7" Tape and Reel 8-Lead MSOP 8-Lead MSOP, 13" Tape and Reel 8-Lead MSOP, 7" Tape and Reel 8-Lead MSOP 8-Lead MSOP, 13" Tape and Reel 8-Lead MSOP, 7" Tape and Reel
Package Option R-8 R-8 R-8 R-8 R-8 R-8 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8
Branding
HBA HBA HBA HBA# HBA# HBA#
Z = Pb-free part, # denotes lead-free product may be top or bottom marked.
Rev. F | Page 23 of 24
AD8138 NOTES
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01073-0-1/06(F)
Rev. F | Page 24 of 24

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